1. Technical Field
The present invention relates to electronic circuits in general, and in particular to frequency divider circuits. Still more particularly, the present invention relates to a single-event upset immune frequency divider circuit.
2. Description of the Related Art
Frequency divider circuits are commonly used in electronic devices that include counting circuits, phase-locked loop circuits, and/or frequency synthesizer circuits. Generally speaking, frequency dividers are used to generate signals of relatively lower frequencies by dividing a high frequency signal already existed within an electronic system. For example, if a 50 MHz signal is desired from a 100 MHz clock signal existed within an electronic system, a frequency divider is used to divide the 100 MHz clock signal by two.
Referring now to the drawings and, in particular, to FIG. 1, there is depicted a block diagram of a frequency divider circuit according to the prior art. As shown, a frequency divider circuit 10 includes a D-type flip-flop circuit 11 and an inverter 12. An input clock signal is applied to a clock input of D-type flip-flop circuit 11, which transitions the logical state of a signal from an output Q to be equal to the logical state of an input signal at an input D when the input clock signal transitions from a logical low state to a logical high state. Inverter 12 applies to the input D a signal that is opposite in logical state to the output signal at output Q so that the output Q changes logical state in response to the rising edge of the input clock signal. As a result, the output signal at the output Q has a frequency that is one half of the input signal frequency.
One problem with prior art frequency divider circuits, such as frequency divider circuit 10, is that they are very susceptible to single-event upsets (SEUs) or single-event transients (SETs) that can result in runt pulses occurred on the clock path and subsequently phase shifts in the output signals. Consequently, it is desirable to provide an SEU immune frequency divider circuit.
In accordance with a preferred embodiment of the present invention, a single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the selected signal output pair of the dual-path multiplexor to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.